2
entity pos is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
y : out STD_LOGIC
);
end pos;
architecture Behavioral of pos is
begin
y <= ( (not a) or b or c ) and
(a or b or c) and
( (not a) or (not b) or (not c) );
end Behavioral;
entity pos is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
y : out STD_LOGIC
);
end pos;
architecture Behavioral of pos is
begin
y <= ( (not a) or b or c ) and
(a or b or c) and
( (not a) or (not b) or (not c) );
end Behavioral;
entity gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y_not : out STD_LOGIC;
y_and : out STD_LOGIC;
y_or : out STD_LOGIC;
y_nand : out STD_LOGIC;
y_nor : out STD_LOGIC;
y_xor : out STD_LOGIC;
y_xnor : out STD_LOGIC);
end gates;
architecture Behavioral of gates is
begin
y_not <= not a;
y_and <= a and b;
y_or <= a or b;
y_nand <= a nand b;
y_nor <= a nor b;
y_xor <= a xor b;
y_xnor <= a xnor b;
end Behavioral;
entity gates_bus is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (6 downto 0));
end gates_bus;
architecture Behavioral of gates_bus is
begin
Y(6) <= not a;
Y(5) <= a and b;
Y(4) <= a or b;
Y(3) <= a nand b;
Y(2) <= a nor b;
Y(1) <= a xor b;
Y(0) <= a xnor b;
-- Y(6 downto 0) <= (not a, a and b, a or b, a nand b, a nor b, a xor b, a xnor b);
-- Y <= (not a, a and b, a or b, a nand b, a nor b, a xor b, a xnor b);
end Behavioral;
entity signals is
Port ( a3, a2, a1, a0 : in STD_LOGIC;
b3, b2, b1, b0 : in STD_LOGIC;
y : out STD_LOGIC);
end signals;
architecture Behavioral_1 of signals is
begin
y <= (a3 xnor b3) and (a2 xnor b2) and (a1 xnor b1) and (a0 xnor b0);
end Behavioral_1;
entity sop is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
y : out STD_LOGIC
);
end sop;
architecture Behavioral of sop is
begin
y <= (a and (not b) and c) or
((not a) and (not b) and c) or
((not a) and b and c) or
((not a) and b and (not c)) or
(a and b and (not c));
end Behavioral;
