3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mx4_1_when_else is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end mx4_1_when_else;
architecture Behavioral of mx4_1_when_else is
begin
y <= D(0) when S = "00" else
D(1) when S = "01" else
D(2) when S = "10" else
D(3) when S = "11";
end Behavioral;
MX4_1
entity mx4_1_when_else is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end mx4_1_when_else;
architecture Behavioral of mx4_1_when_else is
begin
y <= D(0) when S = "00" else
D(1) when S = "01" else
D(2) when S = "10" else
D(3) when S = "11";
end Behavioral;
SHIFTER
entity shifter is
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Mode : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end shifter;
architecture Behavioral of shifter is
constant SHTL : std_logic_vector(1 downto 0) := "00";
constant ROTL : std_logic_vector(1 downto 0) := "01";
constant SHTR : std_logic_vector(1 downto 0) := "10";
constant ROTR : std_logic_vector(1 downto 0) := "11";
component mx4_1_with_select is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end component mx4_1_with_select;
signal Mx3, Mx2, Mx1, Mx0 : std_logic_vector(3 downto 0);
begin
Mx3 <= X(0) & '0' & X(2) & X(2);
MUX3: mx4_1_with_select PORT MAP (
D => Mx3,
S => Mode,
y => Y(3)
);
Mx2 <= X(3) & X(3) & X(1) & X(1);
MUX2: mx4_1_with_select PORT MAP (
D => Mx2,
S => Mode,
y => Y(2)
);
Mx1 <= X(2) & X(2) & X(0) & X(0);
MUX1: mx4_1_with_select PORT MAP (
D => Mx1,
S => Mode,
y => Y(1)
);
Mx0 <= X(1) & X(1) & X(3) & '0';
MUX0: mx4_1_with_select PORT MAP (
D => Mx0,
S => Mode,
y => Y(0)
);
end Behavioral;
entity concurrent_signal_assignment is
Port ( a,b,c : in STD_LOGIC;
y : out STD_LOGIC);
end concurrent_signal_assignment;
architecture Behavioral of concurrent_signal_assignment is
-- Signal declarations
signal not_a_and_not_B : STD_LOGIC;
signal not_b_and_not_c : STD_LOGIC;
signal a_and_b_and_c : STD_LOGIC;
begin
not_a_and_not_B <= (not a) and (not b); -- {0,1}
not_b_and_not_c <= (not b) and (not c); -- (0,4}
a_and_b_and_c <= a and b and c; -- {7}
y <= not_a_and_not_B or not_b_and_not_c or a_and_b_and_c;
end Behavioral;
entity number_representation is
Port ( sign : in STD_LOGIC;
Magnitude : in STD_LOGIC_VECTOR (6 downto 0);
Signed_magnitude : out STD_LOGIC_VECTOR (7 downto 0);
Ones_complement : out STD_LOGIC_VECTOR (7 downto 0);
Twos_complement : out STD_LOGIC_VECTOR (7 downto 0));
end number_representation;
architecture Behavioral of number_representation is
signal Tmp : std_logic_vector(7 downto 0);
begin
Signed_magnitude <= sign & Magnitude;
Tmp <= ('0' & Magnitude) when sign = '0' else ('1' & not(Magnitude));
Ones_complement <= Tmp;
Twos_complement <= Tmp when sign = '0' else std_logic_vector(unsigned(Tmp)+1);
end Behavioral;
