4

 
entity ripple_carry_adder is
    generic(width : positive := 4);
    Port ( A, B : in STD_LOGIC_VECTOR (width-1 downto 0);
           Sum : out STD_LOGIC_VECTOR (width-1 downto 0);
           carry : out STD_LOGIC);
end ripple_carry_adder;
 
architecture Behavioral of ripple_carry_adder is
 
    component half_adder is
        Port ( a, b : in STD_LOGIC;
               sum : out STD_LOGIC;
               carry : out STD_LOGIC);
    end component half_adder;
 
    component full_adder is
        Port ( a, b, c : in STD_LOGIC;
               sum : out STD_LOGIC;
               carry : out STD_LOGIC);
    end component full_adder;
 
signal C : std_logic_vector(width-1 downto 0);
    
begin

entity ripple_carry_adder is

    generic(width : positive := 4);

    Port ( A, B : in STD_LOGIC_VECTOR (width-1 downto 0);

           Sum : out STD_LOGIC_VECTOR (width-1 downto 0);

           carry : out STD_LOGIC);

end ripple_carry_adder;

 

architecture Behavioral of ripple_carry_adder is

 

    component half_adder is

        Port ( a, b : in STD_LOGIC;

               sum : out STD_LOGIC;

               carry : out STD_LOGIC);

    end component half_adder;

 

    component full_adder is

        Port ( a, b, c : in STD_LOGIC;

               sum : out STD_LOGIC;

               carry : out STD_LOGIC);

    end component full_adder;

 

signal C : std_logic_vector(width-1 downto 0);

    

begin

 

RCA : for i in 0 to width-1 generate

LSB : if i = 0 generate

ADD0 : half_adder port map (a => A(0), b => B(0), sum => SUM(0), carry => C(0));

end generate LSB;

 

UPPER_BITS : if i > 0 generate

ADDX : full_adder port map (a => A(i), b => B(i), c => C(i-1), sum => SUM(i), carry => C(i));

end generate UPPER_BITS;

 

end generate RCA;

 

carry <= C(width-1);

 

end Behavioral;

 

entity if_generate is

    generic(sel : natural := 0);

    Port ( a, b, c, d : in  STD_LOGIC;

           y : out  STD_LOGIC);

end if_generate;

 

architecture Behavioral of if_generate is

 

begin

 

    AND_DATA : if sel = 0 generate

        y <= (((a and b) and c) and d);

    end generate;

    

    OR_DATA : if sel = 1 generate

        y <= (((a or b) or c) or d);

    end generate;

    

    NAND_DATA : if sel = 2 generate

        y <= (((a nand b) nand c) nand d);

    end generate;

    

    NOR_DATA : if sel = 3 generate

        y <= (((a nor b) nor c) nor d);

    end generate;

    

    XOR_DATA : if sel = 4 generate

        y <= (((a xor b) xor c) xor d);

    end generate;

    

    XNOR_DATA : if sel >= 5 generate

        y <= (((a xnor b) xnor c) xnor d);

    end generate;

 

end Behavioral;

 
entity mult_6x6s_5x5u is
    Port ( A6s, B6s : in STD_LOGIC_VECTOR (5 downto 0);
           A5u, B5u : in STD_LOGIC_VECTOR (4 downto 0);
           P6s : out STD_LOGIC_VECTOR (11 downto 0);    -- Result in twos complement
           P5u : out STD_LOGIC_VECTOR (9 downto 0));
end mult_6x6s_5x5u;
 
architecture Structural of mult_6x6s_5x5u is
 
    signal A, B : std_logic_vector(17 downto 0);
    signal P : std_logic_vector(35 downto 0);
 
begin
 
    A(17 downto 12) <= A6s;
    A(11 downto 5) <= (others => '0');
    A(4 downto 0) <= A5u;
    
    B(17 downto 12) <= B6s;
    B(11 downto 5) <= (others => '0');
    B(4 downto 0) <= B5u;
 
    -- MULT18X18: 18 x 18 signed asynchronous multiplier
    MULT18X18_inst : MULT18X18 port map (
        P => P, -- 36-bit multiplier output
        A => A, -- 18-bit multiplicand input
        B => B -- 18-bit multiplier input
    );
 
    P6s <= P(35 downto 24);
    P5u <= P(9 downto 0);
 
end Structural;
 
 
entity multiplier is
    Port ( A, B : in STD_LOGIC_VECTOR (17 downto 0);    -- 18-bit multiplicand A and multiplier B 
                                                        -- The Multiplicand is the number taken or multiplied.
                                                        -- The Multiplier is the number denoting how many times the multiplicand is taken.
           P : out STD_LOGIC_VECTOR (35 downto 0));     -- 36-bit multiplier output
end multiplier;
 
--architecture Behavioral of multiplier is
 
--begin
 
--    P <= std_logic_vector(signed(A) * signed(B));
 
--end Behavioral;
 
architecture Structural of multiplier is
 
begin
 
    -- MULT18X18: 18 x 18 signed asynchronous multiplier
    MULT18X18_inst : MULT18X18 port map (
        P => P, -- 36-bit multiplier output
        A => A, -- 18-bit multiplicand input
        B => B  -- 18-bit multiplier input
    );
 
end Structural;

 

entity parity_generator is

    --

    generic(sel : natural := 0;     -- 0 = even parity, 1 = odd parity 

            width : natural := 8    -- data input (word) size

    );  

    Port ( D : in STD_LOGIC_VECTOR (width-1 downto 0);  -- data input

           parity : out STD_LOGIC                       -- parity bit

    );

end parity_generator;

 

architecture Behavioral of parity_generator is

 

begin

 

    --Use for-generate statement to design the "parity_generator" module

 

    EVEN : if sel = 0 generate

    --set the "parity" bit

    end generate;

 

    ODD : if sel = 1 generate

    -- set the "parity" bit

    end generate;

 

end Behavioral;