5
entity d_latch is
Port ( d : in STD_LOGIC;
en : in STD_LOGIC;
q : out STD_LOGIC);
end d_latch;
architecture Behavioral of d_latch is
begin
DFF_LATCH_EN: process(d, en) is
begin
if (en = '1') then
q <= d;
end if;
end process;
end Behavioral;
entity counter is
generic (up_counter : boolean := TRUE;
width : positive := 8;
init_value : natural := 0);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (width-1 downto 0);
o : out STD_LOGIC);
end counter;
architecture Behavioral of counter is
begin
process(clk, rst)
variable cnt : unsigned(width-1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if (rst = '1') then
cnt := to_unsigned(init_value, Y'length);
o <= '0';
else
if (en = '1') then
if up_counter then
cnt := cnt + 1;
else
cnt := cnt - 1;
end if;
if (cnt = 0) then
o <= '1';
else
o <= '0';
end if;
end if;
end if;
end if;
Y <= std_logic_vector(cnt);
end process;
end Behavioral;
entity dff is
Port ( clk : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
DFF_UP: process(clk) is
begin
if rising_edge(clk) then
-- if (clk'event and clk = '1') then
q <= d;
end if;
end process;
end Behavioral;
--architecture Behavioral of dff is
--begin
-- DFF_DOWN: process(clk) is
-- begin
-- if falling_edge(clk) then
---- if (clk'event and clk = '0') then
-- q <= d;
-- end if;
-- end process;
--end Behavioral;
entity dff_en is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC;
en : in STD_LOGIC;
q : out STD_LOGIC);
end dff_en;
architecture Behavioral of dff_en is
begin
DFF_UP_RST_EN: process(clk) is
begin
if rising_edge(clk) then
if (rst = '1') then
q <= '0';
elsif en = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral;
entity mx4_1_case is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end mx4_1_case;
architecture Behavioral of mx4_1_case is
begin
process (D,S)
begin
case S is
when "00" => y <= D(0);
when "01" => y <= D(1);
when "10" => y <= D(2);
when "11" => y <= D(3);
when others => null;
end case;
end process;
end Behavioral;
entity seven_seg_decoder is
Port ( Data : in STD_LOGIC_VECTOR (3 downto 0);
Segments : out STD_LOGIC_VECTOR (6 downto 0));
end seven_seg_decoder;
architecture Behavioral of seven_seg_decoder is
begin
process(Data) begin
case Data is
-- abcdefg
when X"0" => Segments <= "1111110";
when X"1" => Segments <= "0110000";
when X"2" => Segments <= "1101101";
when X"3" => Segments <= "1111001";
when X"4" => Segments <= "0110011";
when X"5" => Segments <= "1011011";
when X"6" => Segments <= "1011111";
when X"7" => Segments <= "1110000";
when X"8" => Segments <= "1111111";
when X"9" => Segments <= "1110011";
when others => Segments <= "0000000";
end case;
end process;
end Behavioral;
entity wide_and is
generic (width : positive := 32); -- data input size
Port ( Data : in STD_LOGIC_VECTOR (width-1 downto 0);
y : out STD_LOGIC);
end wide_and;
architecture Behavioral of wide_and is
begin
process (Data) is
variable tmp : std_logic;
begin
tmp := Data(0);
for i in 1 to width-1 loop
tmp := tmp and Data(i);
end loop;
y <= tmp;
end process;
end Behavioral;