6
entity debouncer is
generic (sys_freq : natural := 100_000_000; -- in Hz
stable_time : natural := 10); -- in ms
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC;
q : out STD_LOGIC);
end debouncer;
architecture Structural of debouncer is
-- Flip-flop D type
component dff is
Port ( clk : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end component dff;
-- Flip-flop D type with enable input
component dff_en is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC;
en : in STD_LOGIC;
q : out STD_LOGIC);
end component dff_en;
component counter is
generic (up_counter : boolean := TRUE;
width : positive := 8;
init_value : natural := 0);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (width-1 downto 0);
o : out STD_LOGIC);
end component counter;
signal q_ff1, q_ff2 : std_logic;
signal en : std_logic;
signal counter_rst : std_logic;
signal detect_zero : std_logic;
begin
FF1 : dff port map (clk => clk, d => btn, q => q_ff1);
FF2 : dff port map (clk => clk, d => q_ff1, q => q_ff2);
counter_rst <= q_ff1 xor q_ff2;
en <= not detect_zero;
CNT : counter generic map (up_counter => false, init_value => ((sys_freq*stable_time)/1000), width => 8) port map (clk => clk, rst => counter_rst, en => en, o => detect_zero);
FF3 : dff_en port map (clk => clk, rst => counter_rst, d => q_ff2, en => detect_zero, q => q);
end Structural;
entity comparator is
generic ( width : positive := 3);
Port ( A, B : in STD_LOGIC_VECTOR (width-1 downto 0);
lt, eq, gt : out STD_LOGIC);
end comparator;
architecture Behavioral_v1 of comparator is
begin
eq <= '1' when A = B else '0';
lt <= '1' when A < B else '0';
gt <= '1' when A > B else '0';
end Behavioral_v1;
--architecture Behavioral_v2 of comparator is
-- signal tmp_eq, tmp_lt : std_logic;
--begin
-- tmp_eq <= '1' when A = B else '0';
-- tmp_lt <= '1' when A < B else '0';
-- gt <= (not tmp_eq) and (not tmp_lt);
-- lt <= tmp_lt;
-- eq <= tmp_eq;
--end Behavioral_v2;
--architecture Structural of comparator is
--signal Tmp_bit_eq, Tmp_eq : std_logic_vector(width-1 downto 0);
--signal Tmp_bit_lt, Tmp_lt : std_logic_vector(width-1 downto 0);
--begin
-- -------------------------------------------
-- ------------------ EQUAL ------------------
-- -------------------------------------------
-- BIT_XNOR : for i in width-1 downto 0 generate
-- Tmp_bit_eq(i) <= A(i) xnor B(i);
-- end generate BIT_XNOR;
-- Tmp_eq(width-1) <= Tmp_bit_eq(width-1);
-- EQUAL : for i in width-2 downto 0 generate
-- Tmp_eq(i) <= Tmp_eq(i+1) and Tmp_bit_eq(i);
-- end generate EQUAL;
-- eq <= Tmp_eq(0);
-- -------------------------------------------
-- --------------- LESS THAN -----------------
-- -------------------------------------------
-- BIT_LESS : for i in width-1 downto 0 generate
-- Tmp_bit_lt(i) <= (not A(i)) and B(i);
-- end generate BIT_LESS;
-- Tmp_lt(width-1) <= Tmp_bit_lt(width-1);
-- LESS : for i in width-2 downto 0 generate
-- Tmp_lt(i) <= Tmp_lt(i+1) or ( Tmp_eq(i+1) and Tmp_bit_lt(i) );
-- end generate LESS;
-- lt <= Tmp_lt(0);
-- -------------------------------------------
-- -------------- GREATER THAN----------------
-- -------------------------------------------
-- gt <= (not Tmp_eq(0)) and (not Tmp_lt(0));
--end Structural;
entity clock_divider is
generic (divider : natural := 100_000_000); -- 1 pulse in every one second
Port ( sys_clk : in STD_LOGIC; -- The base frequency for Basys 3 board (xc7a35tcpg236-1 chip) is 100 MHz
rst : in STD_LOGIC;
clk : out STD_LOGIC);
end clock_divider;
architecture Behavioral of clock_divider is
signal internal_clock : std_logic;
begin
process (rst, sys_clk)
variable clk_divider : natural;
begin
if (rst = '1') then
clk_divider := 0;
internal_clock <= '0';
elsif(rising_edge(sys_clk)) then
if (clk_divider < (divider / 2)) then
clk_divider := clk_divider + 1;
internal_clock <= '0';
elsif (clk_divider = divider-1) then
clk_divider := 0;
internal_clock <= '1';
else
clk_divider := clk_divider + 1;
internal_clock <= '1';
end if;
end if;
end process;
clk <= internal_clock;
end Behavioral;
entity one_hot_encoder is
generic ( width : natural := 4);
Port ( D : in STD_LOGIC_VECTOR (width-1 downto 0);
Y : out STD_LOGIC_VECTOR (width-1 downto 0);
v : out STD_LOGIC);
end one_hot_encoder;
architecture Behavioral of one_hot_encoder is
begin
process(D)
variable OneHot : integer := 0;
begin
Y <= (others => '0');
if unsigned(D) > 0 then
for i in width-1 downto 0 loop
OneHot := i;
exit when D(i) = '1';
end loop;
Y(OneHot) <= '1';
v <= '1';
else
v <= '0';
end if;
end process;
end Behavioral;
entity priority_encoder is
generic ( width : positive := 3);
Port ( D : in STD_LOGIC_VECTOR (width**2-1 downto 0);
Y : out STD_LOGIC_VECTOR (width-1 downto 0);
v : out STD_LOGIC);
end priority_encoder;
architecture Behavioral of priority_encoder is
begin
process(D)
variable OneHot : integer := 0;
begin
Y <= (others => '0');
if unsigned(D) > 0 then
for i in width**2-1 downto 0 loop
OneHot := i;
exit when D(i) = '1';
end loop;
Y <= std_logic_vector(to_unsigned(OneHot, width));
v <= '1';
else
v <= '0';
end if;
end process;
end Behavioral;