7
entity rom_async is
Port ( Addr : in STD_LOGIC_VECTOR (3 downto 0);
Data : out STD_LOGIC_VECTOR (6 downto 0));
end rom_async;
architecture Behavioral of rom_async is
type Memory is array (0 to 15) of std_logic_vector(6 downto 0);
-- Seven-segment display codes
signal ROM : Memory := ("0000001", -- "0"
"1001111", -- "1"
"0010010", -- "2"
"0000110", -- "3"
"1001100", -- "4"
"0100100", -- "5"
"0100000", -- "6"
"0001111", -- "7"
"0000000", -- "8"
"0000100", -- "9"
"0000010", -- a
"1100000", -- b
"0110001", -- C
"1000010", -- d
"0110000", -- E
"0111000" -- F
);
begin
Data <= ROM(to_integer(unsigned(Addr)));
end Behavioral;
entity divisibility_by_3 is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(1 downto 0));
end divisibility_by_3;
architecture Behavioral of divisibility_by_3 is
type states is (S0, S1, S2);
signal state, next_state : states := S0;
begin
--state register
process (clk, rst) is
begin
if rst = '1' then
state <= S0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
-- next state logic
process(state, din) is
begin
case (state) is
when S0 =>
if din = '1' then
next_state <= S1;
else
next_state <= S0;
end if;
when S1 =>
if din = '1' then
next_state <= S0;
else
next_state <= S2;
end if;
when S2 =>
if din = '1' then
next_state <= S2;
else
next_state <= S1;
end if;
when others =>
null;
end case;
end process;
-- output logic
with state select
dout <= "00" when S0,
"01" when S1,
"10" when others;
end Behavioral;
entity robot_moore is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC);
end robot_moore;
architecture Behavioral of robot_moore is
type states is (S0, S1, S2);
signal state, next_state : states := S0;
begin
--state register
process (clk, rst) is
begin
if rst = '1' then
state <= S0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
-- next state logic
process(state, din) is
begin
case (state) is
when S0 =>
if din = '1' then
next_state <= S0;
else
next_state <= S1;
end if;
when S1 =>
if din = '1' then
next_state <= S2;
else
next_state <= S1;
end if;
when S2 =>
if din = '1' then
next_state <= S0;
else
next_state <= S1;
end if;
when others =>
next_state <= S0;
end case;
end process;
-- output logic
dout <= '1' when state = S2 else '0';
end Behavioral;
-- Single port RAM has one input port (i.e. address line) which is used for both storing and retrieving the data
-- Ports:
-- clk : clock signal for synchronous RAM
-- we : enable signal for reading or storing data to the RAM
-- Addr : input port for getting address
-- Din : input data to be stored in RAM
-- Dout : output data read from RAM
--
-- depth : total number of elements to store (put exact number)
-- width : number of bits in each elements
entity single_port_RAM is
generic (depth : positive := 2; width : positive := 3);
Port ( clk : in STD_LOGIC;
we : in STD_LOGIC;
Addr : in STD_LOGIC_VECTOR(depth-1 downto 0);
Din : in STD_LOGIC_VECTOR (width-1 downto 0);
Dout : out STD_LOGIC_VECTOR (width-1 downto 0));
end single_port_RAM;
/*
architecture Behavioral_package of single_port_RAM is
package mem is new work.memories generic map (depth => depth, width => width);
begin
process(clk) is
variable RAM : mem.RAM_type;
attribute ram_style : string;
attribute ram_style of RAM : variable is "block";
begin
if rising_edge(clk) then
if we = '1' then
mem.write_RAM(RAM, Addr, Din);
else
mem.read_RAM(RAM, Addr, Dout);
end if;
end if;
end process;
end Behavioral_package;
*/
architecture Behavioral of single_port_RAM is
type RAM_type is array (2**depth-1 downto 0) of std_logic_vector (width-1 downto 0);
signal RAM : RAM_type;
--attribute ram_style : string;
--attribute ram_style of RAM : signal is "block";
--attribute ram_style of RAM : signal is "distributed";
--attribute ram_style of RAM : signal is "registers";
begin
process(clk) is
begin
if rising_edge(clk) then
if we = '1' then
RAM(to_integer(unsigned(Addr))) <= Din;
end if;
end if;
end process;
Dout <= RAM(to_integer(unsigned(Addr)));
end Behavioral;