8

entity div is

    generic(width : positive := 4);

    Port (Numerator : in  STD_LOGIC_VECTOR (width-1 downto 0);

          Denominator : in  STD_LOGIC_VECTOR (width-1 downto 0);

          input_rdy : in  STD_LOGIC;

          clk, rst : in  STD_LOGIC;

          Quotient : out  STD_LOGIC_VECTOR (width-1 downto 0);

          Remainder : out  STD_LOGIC_VECTOR (width-1 downto 0);

          done : out STD_LOGIC);

end div;

architecture Behavioral of div is

    type states is (IDLE, INIT, TEST_PC, TEST_QB, SUBSET, SHIFT, FINE);

    signal state, next_state : states := IDLE; 

    signal op_init, op_shift, op_sub, op_set_lsb : std_logic;

    signal R, Q : unsigned(width-1 downto 0);

    signal PC : integer range 0 to width;

begin

    -- Control Unit

    STATE_REG : process(clk, rst) is

    begin

        if rst = '1' then

            state <= IDLE;

        elsif rising_edge(clk) then

            state <= next_state;

        end if;

    end process;

    PC_REG : process(clk) is

    begin

        if rising_edge(clk) then

            if state = IDLE then

                PC <= 0;

            elsif state = INIT then

                PC <= width;

            elsif state = SHIFT then

                PC <= PC - 1;

            end if;

        end if;

    end process;

    NEXT_STATE_LOGIC : process (state, input_rdy, R, Denominator, PC) is

    begin

        case state is

            when IDLE =>

                if input_rdy = '1' then

                    next_state <= INIT;

                else

                    next_state <= IDLE;

                end if;

            when INIT => 

                next_state <= TEST_PC;

            when TEST_PC => 

                if PC = 0 then

                    next_state <= FINE;

                else

                    next_state <= SHIFT;

                end if;

            when SHIFT =>

                    next_state <= TEST_QB;

            when TEST_QB =>

                    if R < unsigned(Denominator) then

                        next_state <= TEST_PC;

                    else

                        next_state <= SUBSET;

                    end if;

            when SUBSET =>

                    next_state <= TEST_PC;

            when FINE =>

                    next_state <= IDLE;

            when others => 

                    next_state <= state;

        end case;

    end process;

    OUTPUT_LOGIC : process (state) is

    begin

        op_init <= '0'; op_shift <= '0'; op_sub <= '0'; op_set_lsb <= '0';

        case state is

            when INIT =>

                op_init <= '1';

            when SHIFT =>

                op_shift <= '1';

            when SUBSET =>

                op_sub <= '1';

                op_set_lsb <= '1';

            when others => null;

        end case;

    end process;

-- Operating/Processing Unit

Quotient <= std_logic_vector(Q);

Remainder <= std_logic_vector(R);

done <= '1' when state = FINE else '0' ;

R_REG : process (clk) is

begin

if rising_edge(clk) then

if op_init = '1' then

R <= (others => '0');

elsif op_shift = '1' then

R <= R(width-2 downto 0) & Q(width-1);

elsif op_sub = '1' then

R <= R - unsigned(Denominator);

end if;

end if;

end process;

Q_REG : process (clk) is

begin

if rising_edge(clk) then

if op_init = '1' then

Q <= unsigned(Numerator);

elsif op_shift = '1' then

Q <= Q(width-2 downto 0) & '0';

elsif op_set_lsb = '1' then

Q(0) <= '1';

end if;

end if;

end process;

end Behavioral;