be

 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity pos_tb is
--  Port ( );
end pos_tb;
 
architecture Behavioral of pos_tb is
    
    component pos
    Port (
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        c : in STD_LOGIC;
        y : out STD_LOGIC);
    end component pos;
    
    signal a : std_logic :='0';
    signal b : std_logic :='0';
    signal c : std_logic :='0';
    
    signal y : std_logic;
    
    
    signal sim_a : std_logic :='0';
    signal sim_b: std_logic := '0';
    signal sim_c: std_logic := '0';
    constant period : time := 200 ns; 
    
begin
    UUT: pos port map (a, b, c, y);
    
    generate_a: process
    begin
        sim_a <= '0';
        wait for period;
        sim_a <= '1';
        wait for period;
    end process;
 
    generate_b: process
    begin
        sim_b <= '0';
        wait for period/2;
        sim_b <= '1';
        wait for period/2;
    end process;
    
    generate_c: process
        begin
            sim_c <= '0';
            wait for period/4;
            sim_c <= '1';
            wait for period/4;
        end process;
 
    a <= sim_a;
    b <= sim_b;
    c <= sim_c;
 
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity pos_tb is
--  Port ( );
end pos_tb;
 
architecture Behavioral of pos_tb is
    
    component pos
    Port (
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        c : in STD_LOGIC;
        y : out STD_LOGIC);
    end component pos;
    
    signal a : std_logic :='0';
    signal b : std_logic :='0';
    signal c : std_logic :='0';
    
    signal y : std_logic;
    
    
    signal sim_a : std_logic :='0';
    signal sim_b: std_logic := '0';
    signal sim_c: std_logic := '0';
    constant period : time := 200 ns; 
    
begin
    UUT: pos port map (a, b, c, y);
    
    generate_a: process
    begin
        sim_a <= '0';
        wait for period;
        sim_a <= '1';
        wait for period;
    end process;
 
    generate_b: process
    begin
        sim_b <= '0';
        wait for period/2;
        sim_b <= '1';
        wait for period/2;
    end process;
    
    generate_c: process
        begin
            sim_c <= '0';
            wait for period/4;
            sim_c <= '1';
            wait for period/4;
        end process;
 
    a <= sim_a;
    b <= sim_b;
    c <= sim_c;
 
end Behavioral;
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity mx4_1_when_else_tb is
--  Port ( );
end mx4_1_when_else_tb;
 
architecture Behavioral of mx4_1_when_else_tb is
 
    -- Component Declaration for the Unit Under Test (UUT)
    component mx4_1_when_else is
        Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
               S : in STD_LOGIC_VECTOR (1 downto 0);
               y : out STD_LOGIC);
    end component mx4_1_when_else;
 
    --Inputs
    signal D : std_logic_vector(3 downto 0) := "0000";
    signal S : std_logic_vector(1 downto 0) := "00";
    
    --Outputs
    signal y : std_logic;
 
begin
 
    -- Instantiate the Unit Under Test (UUT)
    UUT: mx4_1_when_else port map (
          D => D,
          S => S,
          y => y
        );
 
    process
    begin
        S(0) <= '0';
        wait for 10 ns;
        S(0) <= '1';
        wait for 10 ns;        
    end process;
 
    process
    begin
        S(1) <= '0';
        wait for 20 ns;
        S(1) <= '1';
        wait for 20 ns;        
    end process;
 
    -- Stimulus process
    stim_proc: process
    begin        
 
        -- Hold reset state for 80 ns.
        wait for 80 ns;    
 
        D <= "0000", 
             "0001" after 40 ns, 
             "0010" after 80 ns, 
             "0011" after 120 ns, 
             "0100" after 160 ns, 
             "0101" after 200 ns, 
             "0110" after 240 ns, 
             "0111" after 280 ns, 
             "1000" after 320 ns,                          
             "1001" after 360 ns,                          
             "1010" after 400 ns,                          
             "1011" after 440 ns,                          
             "1100" after 480 ns,                          
             "1101" after 520 ns,                          
             "1110" after 560 ns,                          
             "1111" after 600 ns;                          
        wait;
    end process;
 
end Behavioral;
 
 
 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

 

entity multiplier_tb is

--  Port ( );

end multiplier_tb;

 

architecture Behavioral of multiplier_tb is

 

    -- Component Declaration for the Unit Under Test (UUT)

    component multiplier is

        Port ( A, B : in STD_LOGIC_VECTOR (17 downto 0);

               P : out STD_LOGIC_VECTOR (35 downto 0));

    end component multiplier;

 

    --Inputs

    signal A : std_logic_vector(17 downto 0) := (others => '0');

    signal B : std_logic_vector(17 downto 0) := (others => '0');

 

      --Outputs

    signal P : std_logic_vector(35 downto 0) := (others => '0');

 

begin

 

    -- Instantiate the Unit Under Test (UUT)

    UUT: multiplier PORT MAP (A => A, B => B, P => P);

    

    -- Stimulus process

    stim_proc : process

    begin

    end process;        

    

end Behavioral;